Utilize este identificador para referenciar este registo:
https://hdl.handle.net/1822/87678
Título: | CVA6 RISC-V virtualization: architecture, microarchitecture, and design space exploration |
Autor(es): | Sá, Bruno Valente, Luca Martins, José Carvalho Rossi, Davide Benini, Luca Pinto, Sandro |
Palavras-chave: | Virtualization CVA6 Microarchitecture TLB MMU Design space exploration Hypervisor RISC-V design space exploration (DSE) memory management unit (MMU) translation lookaside buffer (TLB) |
Data: | 2023 |
Editora: | Institute of Electrical and Electronics Engineers (IEEE) |
Revista: | Ieee Transactions on Very Large Scale Integration (vlsi) Systems |
Resumo(s): | Virtualization is a key technology used in a wide range of applications, from cloud computing to embedded systems. Over the last few years, mainstream computer architectures were extended with hardware virtualization support, giving rise to a set of virtualization technologies (e.g., Intel VT, Arm VE) that are now proliferating in modern processors and SoCs. In this article, we describe our work on hardware virtualization support in the RISC-V CVA6 core. Our contribution is multifold and encompasses architecture, microarchitecture, and design space exploration. In particular, we highlight the design of a set of microarchitectural enhancements (i.e., G-Stage Translation Lookaside Buffer (GTLB), L2 TLB) to alleviate the virtualization performance overhead. We also perform a Design Space Exploration (DSE) and accompanying post-layout simulations (based on 22nm FDX technology) to assess Performance, Power,and Area (PPA). Further, we map design variants on an FPGA platform (Genesys 2) to assess the functional performance-area trade-off. Based on the DSE, we select an optimal design point for the CVA6 with hardware virtualization support. For this optimal hardware configuration, we collected functional performance results by running the MiBench benchmark on Linux atop Bao hypervisor for a single-core configuration. We observed a performance speedup of up to 16% (approx. 12.5% on average) compared with virtualization-aware non-optimized design at the minimal cost of 0.78% in area and 0.33% in power. Finally, all work described in this article is publicly available and opensourced for the community to further evaluate additional design configurations and software stacks |
Tipo: | Artigo |
URI: | https://hdl.handle.net/1822/87678 |
DOI: | 10.1109/TVLSI.2023.3302837 |
ISSN: | 1063-8210 |
e-ISSN: | 1557-9999 |
Versão da editora: | https://ieeexplore.ieee.org/document/10233226 |
Arbitragem científica: | yes |
Acesso: | Acesso aberto |
Aparece nas coleções: | CAlg - Artigos em revistas internacionais / Papers in international journals |
Ficheiros deste registo:
Ficheiro | Descrição | Tamanho | Formato | |
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2302.02969.pdf | 2,52 MB | Adobe PDF | Ver/Abrir |