On-chip array of thermoelectric peltier microcoolers

Abstract

This article reports on the theoretical modelling, the Finite Element Modelling (FEM) simulation, the fabrication process and preliminary results of the first on-chip thermoelectric microcooler array (64 pixels arranged in a 8×8 array), with each pixel independently controlled. This microcooler array uses co-evaporated V–VI compounds of Bi2Te3 and Sb2Te3 as thermoelectric layers, and can be fabricated using planar thin-film technology, lithography and wet etching, on top of a silicon wafer where the CMOS electronic circuits were previously made.