Condition codes evaluation on dynamic binary translation for embedded platforms

Abstract

A widely recognized issue when implementing dynamic binary translation is the condition codes (CCs) or flag bits emulation. The authors in the literature have approached this problem with software optimization techniques based on dataflow analysis, instruction set architecture (ISA) extensions and additional dedicated hardware, i.e., field-programmable gate array. We introduce a novel technique to handle CCs using commercial off-the-shelf architectural debug hardware as a triggering mechanism while assessing and comparing it with two existent CCs evaluation methods on the resource-constrained embedded systems arena. Our method is functionality-wise comparable with reconfigurable hardware modules or ISA extensions in open architectures and is source architecture independent, with possible applications in other use scenarios, such as application debugging and instrumentation.