Utilize este identificador para referenciar este registo: https://hdl.handle.net/1822/50793

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dc.contributor.authorLourenço, Cláudio Filipe Belo Silvapor
dc.contributor.authorLamraoui, Si-Mohamedpor
dc.contributor.authorNakajima, Shinpor
dc.contributor.authorPinto, Jorge Sousapor
dc.date.accessioned2018-02-21T14:50:37Z-
dc.date.available2018-02-21T14:50:37Z-
dc.date.issued2015-
dc.identifier.citationC.B.Lourenço, S.Lamraoui, S.Nakajima,and J.S.Pinto. Studying Verification Conditions for Imperative Programs. In G. Grov and A. Ire- land, editors, Proceedings of the 15th International Workshop on Automated Verification of Critical Systems (AVOCS’15), volume 72 of Electronic Communications of the EASST, 2015. European Association of Software Science and Technology.por
dc.identifier.issn1863-2122-
dc.identifier.urihttps://hdl.handle.net/1822/50793-
dc.description.abstractProgram verification tools use verification condition generators to produce logical formulas whose validity implies that the program is correct with respect to its specification. Different tools produce different conditions, and the underlying algorithms have not been properly exposed or explored so far. In this paper we consider a simple imperative programming language, extended with assume and assert statements, to present different ways of generating verification conditions. We study the approaches with experimental results originated by verification conditions generated from the intermediate representation of LLVM.por
dc.description.sponsorshipThis work is partially financed by the FCT – Fundação para a Ciência e a Tecnologia (Portuguese Foundation for Science and Technology) within project UID/EEA/50014/2013 and by the NII International Internship Program.por
dc.description.sponsorshipSFRH/BD/52236/2013por
dc.language.isoengpor
dc.publisherEuropean Association of Software Science and Technology (EASST)por
dc.relationinfo:eu-repo/grantAgreement/FCT/5876/147326/PTpor
dc.rightsopenAccesspor
dc.rights.urihttp://creativecommons.org/licenses/by/4.0/por
dc.subjectVerification Conditionspor
dc.subjectLLVMpor
dc.subjectSingle-assignment formpor
dc.subjectSoftware verificationpor
dc.subjectBounded verificationpor
dc.subjectSingle-assignmentpor
dc.titleStudying verification conditions for imperative programspor
dc.typearticlepor
dc.peerreviewedyespor
oaire.citationStartPage1por
oaire.citationEndPage15por
oaire.citationVolume72por
dc.identifier.doi10.14279/tuj.eceasst.72.1011por
dc.subject.fosCiências Naturais::Ciências da Computação e da Informaçãopor
dc.description.publicationversioninfo:eu-repo/semantics/publishedVersionpor
sdum.journalElectronic Communications of the EASSTpor
sdum.conferencePublicationProceedings of the 15th International Workshop on Automated Verification of Critical Systems (AVOCS’15)por
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