LP805X : a customizable and low power 8051 soft core for FPGA applications

Abstract

In today's advanced technological age, embedded and real time systems have become ubiquitous, covering a wide range of applicability. As a result there is an ever growing need for low power capabilities along with reasonable performance, thus presenting a virtual demand for power-aware devices. The purpose of this work was leveraging key techniques and technologies such as design laziness, componentware design, generative design, separation of mechanism and policy, voltage-frequency island, state encoding, clock gating, and operand isolation, and then investigating their effects while designing an energy and power-conscious microcontroller based on 8051 ISA (Instruction Set Architecture) without disregard to silicon area, required application functionalities and performance. Simulations show that our purposed 2 stage pipeline system with built-in hybrid scheduler operates at 230μW@1MHz.