Utilize este identificador para referenciar este registo:
https://hdl.handle.net/1822/2029
Registo completo
Campo DC | Valor | Idioma |
---|---|---|
dc.contributor.author | Tavares, Adriano | - |
dc.contributor.author | Couto, Carlos | - |
dc.date.accessioned | 2005-06-08T13:12:12Z | - |
dc.date.available | 2005-06-08T13:12:12Z | - |
dc.date.issued | 2001-11 | - |
dc.identifier.citation | ANNUAL CONFERENCE OF THE IEEE INDUSTRIAL ELECTRONICS SOCIETY, 27, DENVER, 2001. | eng |
dc.identifier.uri | https://hdl.handle.net/1822/2029 | - |
dc.description.abstract | Current VLSI and networking technology, the increase in computational power, and the rapid decrease in computational cost, enable the interconnection of VLSI processors, which can be arranged on a functional decomposition of the computational task to exploit the potential of multiprocessing. The use of multiprocessor systems in such way, provides a novel and cost effective solution in solving many practical problems in signal processing, control systems, instrumentation systems and robotics. In this article we present a framework that addresses the specificities of industrial processors, such as DSPs and microcontrollers and can easily be used to implement a huge range of scheduling algorithms. | eng |
dc.language.iso | eng | eng |
dc.publisher | IEEE | eng |
dc.rights | openAccess | eng |
dc.subject | Scheduling | eng |
dc.subject | Heterogeneous multiprocessor system | eng |
dc.subject | Embedded systems | eng |
dc.subject | Tabu search method | eng |
dc.subject | Optimization methods | eng |
dc.subject | Interprocessor communication modeling | eng |
dc.title | A scheduling framework for heterogenous multiprocessor architectures based on industrial processors (DSP and microcontrollers) | eng |
dc.type | conferencePaper | eng |
dc.peerreviewed | yes | eng |
Aparece nas coleções: | DEI - Artigos em atas de congressos internacionais |
Ficheiros deste registo:
Ficheiro | Descrição | Tamanho | Formato | |
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IECON2001_final.pdf | 137,02 kB | Adobe PDF | Ver/Abrir |