Utilize este identificador para referenciar este registo:
https://hdl.handle.net/1822/1619
Título: | An integrated folded-patch chip-size antenna using high-resistivity polycrystalline silicon substrate |
Autor(es): | Mendes, P. M. Polyakov, A. Bartek, M. Burghartz, J. N. Correia, J. H. |
Palavras-chave: | Integrated antenna Folded antenna Small antenna Wireless microsystem |
Data: | Out-2004 |
Editora: | IEEE |
Citação: | ASDAM. INTERNATIONAL CONFERENCE ON ADVANCED SEMICONDUCTOR DEVICES AND MICROSYSTEMS, 5, Smolenice Castle, 2004 - "Proceedings". Piscataway : IEEE, 2004. ISBN 0-7803-8535-7. p. 311-314. |
Resumo(s): | High-resistivity polycrystalline silicon (HRPS) wafers are utilized as low-loss substrates for three-dimensional integration of on-chip antennas in wafer-level chip-scale packages (WLCSP). Sandwiching of HRPS and silicon wafers enables to integrate complex RF passives with a spacing of >150 µm to the conductive silicon substrate containing the circuitry, while providing mechanical stability, reducing form factor and avoiding any additional RF loss. A folded-patch antenna with dimensions of 2.5x2.5x1 mm3, operating at 5.7 GHz was analysed considering a 10 kΩ-cm HRPS wafer. The antenna has a –10 dB return loss bandwidth of 50 MHz and an efficiency of 58 %, a performance comparable to glass substrates. |
Tipo: | Artigo em ata de conferência |
URI: | https://hdl.handle.net/1822/1619 |
ISBN: | 0-7803-8535-7 |
Arbitragem científica: | yes |
Acesso: | Acesso aberto |
Aparece nas coleções: | DEI - Artigos em atas de congressos internacionais |
Ficheiros deste registo:
Ficheiro | Descrição | Tamanho | Formato | |
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slovakia_PM.pdf | 304,34 kB | Adobe PDF | Ver/Abrir |