A FPGA based C runtime hardware accelerator

Abstract

As the complexity of embedded systems, as well as the range of applications, grows, the demand for low power high-performance systems also increases. Solutions to address these issues have been presented in the literature, addressing techniques to increase performance by replacing software features, namely RTOS primitives, by hardware implementations. This paper presents an acceleration technique at a lower level: the runtime environment. Hardwiring part of a programming language’s runtime environment decreases the required time to perform a task, offering acceleration at a low-level, transparent to higher-level layers. The developed technique was implemented on a FPGA based RISC processor; experimental results showed a decrease in the time required to perform a given task of up to 16%.