Utilize este identificador para referenciar este registo:
https://hdl.handle.net/1822/5976| Título: | VHDL generation from hierarchical petri net specifications of parallel controllers |
| Autor(es): | Fernandes, João M. Adamski, Marian Proença, Alberto José |
| Palavras-chave: | VHDL generation Parallel controllers Petri nets |
| Data: | Mar-1997 |
| Editora: | Institution of Electrical Engineers (IEE) |
| Revista: | Iee Proceedings-Computers and Digital Techniques |
| Citação: | "IEE Proceedings : Computers and Digital Techniques". ISSN 1350-2387. 144:2 (Mar. 1997) 127-137. |
| Resumo(s): | Parallel controllers can be best specified using a description with a formal support to validate structural and dynamic properties. Petri Nets (PN) can provide an adequate means to model and to animate parallel systems based on the control and data path approach, in a hierarchically structured way. A set of tools was developed to allow formal validation of parallel controllers, based on hierarchical PN-based specifications and to automatically generate RT-level VHDL code. An example of a VLSI chip design, the transputer link adaptor, shows the capabilities of this methodology and associated tools. |
| Tipo: | Artigo |
| URI: | https://hdl.handle.net/1822/5976 |
| DOI: | 10.1049/ip-cdt:19970845 |
| ISSN: | 1350-2387 |
| Arbitragem científica: | yes |
| Acesso: | Acesso aberto |
| Aparece nas coleções: | DI/CCTC - Artigos (papers) |
Ficheiros deste registo:
| Ficheiro | Descrição | Tamanho | Formato | |
|---|---|---|---|---|
| 1997-IEECDT.pdf | 999 kB | Adobe PDF | Ver/Abrir |
