Please use this identifier to cite or link to this item: http://hdl.handle.net/1822/5976

TitleVHDL generation from hierarchical petri net specifications of parallel controllers
Author(s)Fernandes, João M.
Adamski, Marian
Proença, Alberto José
KeywordsVHDL generation
Parallel controllers
Petri nets
Issue dateMar-1997
PublisherInstitution of Electrical Engineers (IEE)
JournalIee Proceedings-Computers and Digital Techniques
Citation"IEE Proceedings : Computers and Digital Techniques". ISSN 1350-2387. 144:2 (Mar. 1997) 127-137.
Abstract(s)Parallel controllers can be best specified using a description with a formal support to validate structural and dynamic properties. Petri Nets (PN) can provide an adequate means to model and to animate parallel systems based on the control and data path approach, in a hierarchically structured way. A set of tools was developed to allow formal validation of parallel controllers, based on hierarchical PN-based specifications and to automatically generate RT-level VHDL code. An example of a VLSI chip design, the transputer link adaptor, shows the capabilities of this methodology and associated tools.
Typearticle
URIhttp://hdl.handle.net/1822/5976
DOI10.1049/ip-cdt:19970845
ISSN1350-2387
Peer-Reviewedyes
AccessopenAccess
Appears in Collections:DI/CCTC - Artigos (papers)
CAlg - Artigos em revistas internacionais/Papers in international journals

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