Please use this identifier to cite or link to this item: http://hdl.handle.net/1822/36868

TitleCo-designed FreeRTOS deployed on FPGA
Author(s)Pereira, J.
Oliveira, D.
Pinto, S.
Cardoso, Nuno
Silva, V.
Gomes, T.
Mendes, José A.
Cardoso, Paulo
KeywordsReal-time Systems
Determinism, Latency
FreeRTOS
Hardware Accelerators
Determinism
Latency
Issue date2015
PublisherIEEE
JournalBrazilian Symposium on Computing System Engineering
CitationPereira, J., Oliveira, D., Pinto, S., Cardoso, N., Silva, V., Gomes, T., . . . Cardoso, P. (2015). Co-Designed FreeRTOS Deployed on FPGA. Paper presented at the Brazilian Symposium on Computing System Engineering, SBESC.
Abstract(s)Most embedded systems are bound to real-time constraints. Two of the critical metrics presented in these systems are determinism and latency. Due to growing in complexity of embedded applications, real time operating systems (RTOS) are needed, not only to hide the increasingly complex hardware, but also to provide services to the system’s running tasks. Unfortunately, this new layer on an embedded system puts more pressure on the aforementioned metrics. One of the ways to cope with this problem is to offload RTOS run-time services to the hardware layer. This paper presents a hybrid hardware/software implementation of this technique upon the well known FreeRTOS, improving system’s latency and predictability, by migrating critical runtime services to hardware. The developed hardware accelerators were synthesized on a field-programmable gate array (FPGA), exploiting the point-to-point bus Fast Simplex Link (FSL) to interconnect to the Xilinx’s Microbaze soft-core processor.
TypeConference paper
URIhttp://hdl.handle.net/1822/36868
ISBN9781479985593
DOI10.1109/SBESC.2014.11
ISSN2324-7886
Publisher versionhttp://sbesc.lisha.ufsc.br/sbesc2014/Proceedings
Peer-Reviewedyes
AccessOpen access
Appears in Collections:CAlg - Artigos em livros de atas/Papers in proceedings

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