Please use this identifier to cite or link to this item: http://hdl.handle.net/1822/1634

TitleWafer-level integration of on-chip antennas and RF passives using high-resistivity polysilicon substrate technology
Author(s)Mendes, P. M.
Sinaga, S. M.
Polyakov, A.
Bartek, M.
Burghartz, J. N.
Correia, J. H.
KeywordsWafer level integration
On-chip antennas
Wireless microsystems
Issue dateJun-2004
PublisherIEEE
JournalProceedings - Electronic Components and Technology Conference
CitationECTC. ELECTRONICS COMPONENTS AND TECHNOLOGY CONFERENCE, 54, Las Vegas, 2004 - "Proceedings". Piscataway : IEEE, 2004. ISBN 0-7803-8365-6. p. 1879-1884.
Abstract(s)High-resistivity polycrystalline silicon (HRPS) wafers are utilized as low-loss substrates for three-dimensional integration of on-chip antennas and RF passive components (e.g. large inductors) in wafer-level chip-scale packages (WLCSP). Sandwiching of HRPS and silicon wafers enables to integrate large RF passives with a spacing of >150 µm to the conductive silicon substrate containing the circuitry, while providing mechanical stability, reducing form factor and avoiding any additional RF loss. Antenna performance comparable to glass substrates and high quality factors for large spiral inductors (Q=11 at 1 GHz; 34 nH) are demonstrated. The HRPS substrates have high dielectric constant, low RF loss, high thermal conductivity, perfect thermal matching, and processing similar to singlecrystalline silicon.
TypeConference paper
URIhttp://hdl.handle.net/1822/1634
ISBN0-7803-8365-6
ISSN0569-5503
Peer-Reviewedyes
AccessOpen access
Appears in Collections:DEI - Artigos em atas de congressos internacionais

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