Folded-patch chip-size antennas for wireless microsystems using wafer-level chip-scale packaging

Abstract

This paper reports on design and fabrication options of an integrated folded shorted-patch chip-size antenna for applications in short-range wireless microsystems. The antenna is built using a stack of two adhesively bonded wafers with patterned metallization and through-wafer electrical interconnects. Different fabrication options based on via formation in glass and/or high-resistivity silicon substrates using excimer laser ablation or powder blasting are analyzed.